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Electrical Characteristics
Table 36. PCI AC Timing Specifications (continued)
33 MHz
66 MHz
Parameter
Symbol
Unit
Min
Max
Min
Max
Notes:
1.
2.
3.
4.
5.
See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
All PCI signals are measured from 0.5 × V DDIO of the rising edge of PCI_CLK_IN to 0.4 × V DDIO of the signal in question for
3.3-V PCI signaling levels.
For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Input timings are measured at the pin.
The reset assertion timing requirement for HRESET is in Table 19 and Figure 7
Figure 15 provides the AC test load for the PCI.
Output
Z 0 = 50 Ω
R L = 50 Ω
V DD /2
Figure 15. PCI AC Test Load
Figure 16 shows the PCI input AC timing conditions.
CLK
t PCSU
t PCH
Input
Figure 16. PCI Input AC Timing Measurement Conditions
Figure 17 shows the PCI output AC timing conditions.
CLK
t PCVAL
Output Delay
t PCOFF
t PCON
High-Impedance
Output
Figure 17. PCI Output AC Timing Measurement Condition
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
51
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